水果制品许可证审查细则.ppt

3D-TSV 测试调研报告
马鹤
2011/8/13
3D stacked ICs
To address the ever increasing need for low cost, high density devices a new industry design paradigm has emerged. 3D stacked IC (SIC) using Through Silicon Via (TSV) interconnects offers the opportunity to integrate multiple ICs at lower cost and silicon footprint than conventional System in Package (SiP) technologies.
Due to the new advanced manufacturing processes and physical access limitations of the TSVs, it is necessary for us to know the new characterizations of the TSVs.
Test Content
Electrical Characterization of 3D TSV
Ⅰ、TSV DC characterization
Ⅱ、AC characterization
Ⅲ、High frequency characterization
Equivalent thermal conductivity of TSV
Test for 3D chips
Ⅰ、DC Characterization
A. TSV resistance
For an accurate measurement of TSV resistance, 4-point Kelvin resistor configurations are adopted
DC Characterization
isolated TSVs show some voids or interfaces between the TSV and the landing pad, which are affecting the TSV contact resistance. This problem is absent in the dense TSV structures; causes are still under investigation.
DC Characterization
B. TSV yield
TSV matrix structures where each TSV in the array is accessible for electrical measurement have been implemented.
DC Characterization
Measurement results for a 8x8 TSV matrix with a) 10um and b) 20um pitch. TSV yield decreases with TSV pitch and is lower at the edge of both matrices. TSVs in the center of the array show a good contact with the landing pad; some Cu extrusion due to bonding is visible.
A possible cause maybe occurs in the procedure of thinning the wafer, when some particles generated in the procedure were left in the peripheral TSVs.
DC Characterization
current
The same matrix concept is extended to measure the leakage current to Si substrate and the breakdown voltage of each TSV insulator in the array by providing a substrate contact in proximity of each TSV; in this case, the landing pad connection is not neces