基于vhdl时钟设计说明书.doc

12/24小时数字钟设计顶层图
12/24小时数字钟设计顶层图
二、模块和程序
1、计数器25000
library ieee;
use ;
use ;
entity t25000 is
port(clk:in std_logic;
clkout:out std_logic);
end t25000;
architecture bav of t25000 is
t:integer range 0 to 24999;
begin
process(clk)
begin
if clk'event and clk='1' then
t=24999 then
cnt<=0;
else
cnt<=cnt+1;
end if;
t<12500 then
clkout<='1';
else
clkout<='0';
end if;
end if;
end process;
end bav;
2、去抖模块
library ieee;
use ;
use ;
entity yourname_qudou is
port(key_in,clk_1kHz:in std_logic;
key_out:out std_logic);
end yourname_qudou;
architecture behav of yourname_qudou is
t20:integer range 0 to 19;
begin
process(clk_1kHz,key_in)
begin
if clk_1kHz'event and clk_1kHz='1' then
t20=19 then
cnt20<=0;
key_out<=key_in;
else
cnt20<=cnt20+1;
end if;
end if;
end process;
end behav;
3、万年历模块
万年历顶层电路图
①年月日星期模块
library ieee;
use ;
use ;
entity yourname_ymdx is
port(
preset:in std_logic;
co:in std_logic;
date: out std_logic_vector(7 downto 0);
month,year:out std_logic_vector(7 downto 0);
xingqi:out std_logic_vector(3 downto 0));
end yourname_ymdx;
architecture bav of yourname_ymdx is
signal yue:std_logic_vector(7 downto 0):="00000001";
signal nian:std_logic_vector(7 downto 0):="00001100";
signal ri:std_logic_vector(7 downto 0):="00001100";
signal xingqi1:std_logic_vector(3 downto 0):="0010";
t:std_logic_vector(7 downto 0):="00000000";
signal qm:integer range 28 to 31;
begin
process(yue,nian)
begin
case yue is
when "00000001"=>qm<=31;
when "00000010"=>
if (nian(0)='0') and (nian(1)='0') then qm<=29;
else qm<=28; end if;
when"00000011"=>qm<=31;
when"00000100"=>qm<=30;
when"00000101"=>qm<=31;
when"00000110"=>qm<=30;
when"00000111"=>qm<=31;
when"00001000"=>qm<=31;
when"00001001"=>qm<=30;
when"00001010