Verilog HDL.pdf

ASICs...THE COURSE (1 WEEK)
VERILOG HDL 11
Key terms and concepts: syntax and semantics • operators • hierarchy • procedures and assign-
ments • timing controls and delay • tasks and functions • control statements • logic-gate modeling
• modeling delay • altering parameters • other Verilog features: PLI
History: Gateway Design Automation developed Verilog as a simulation language • Cadence
purchased Gateway in 1989 • Open Verilog International (OVI) was created to develop the
Verilog language as an IEEE standard • Verilog LRM, IEEE Std 1364-1995 • problems with a
normative LRM
A Counter
Key terms and concepts: Verilog keywords • simulation language • compilation • interpreted,
compiled, and native code simulators
`timescale 1ns/1ns // Set the units of time to be nanoseconds. //1
module counter; //2
reg clock; // Declare a reg data type for the clock. //3
integer count; // Declare an integer data type for the count. //4
initial // Initialize things; this executes once at t=0. //5
begin //6
clock = 0; count = 0; // Initialize signals. //7
#340 $finish; // Finish after 340 time ticks. //8
end //9
/* An always statement to generate the clock; only one statement
follows the always so we don't need a begin and an end. */ //10
always //11
#10 clock = ~ clock; // Delay (10ns) is set to half the clock
cycle. //12
/* An always statement to do the counting; this executes at the same
time (concurrently) as the preceding always statement. */ //13
always //14
begin //15
1
2 SECTION 11 VERILOG HDL ASICS... THE COURSE
// Wait here until the clock goes from 1 to 0. //16
@ (negedge clock); //17
// Now handle the counting. //18
if (count == 7) //19
count = 0; //20
else //21
count = count + 1; //22
$display("time = ",$time," count = ", count); //23
end //24
endmodule //25
Basics of the Verilog Language
Key terms and concepts: identifier • Verilog is case-sensitive • system tasks and functions
begin with a dollar