Quartus II Software Design Series: Verification Debugging Tools – SignalTap II Embedded Logic Analyzer 2 SignalTap II Embedded Logic Analyzer Captures the logic state of FPGA internal signals using a defined clock signal Gives designers ability to monitor buried signals Connects to Quartus II software through FPGA JTAG connection Captures real-time data on rising edges of sampling clock Available for free Installed with full subscription or web edition Installed with stand-alone programmer 3 When to Use SignalTap II ELA No external equipment available Design targets FPGA Additional device resources available for analyzer Logic blocks Memory blocks JTAG connection available Performing functional debug 4 SignalTap II ELA Agenda SignalTap II ELA overview & features Using SignalTap II ELA interface Additional SignalTap II ELA features 5 How Does it Work? Configure ELA Download ELA into FPGA along with design Start running ELA Defined trigger event(s) Samples and stores internal signal states in device memory Captured samples transferred to Quartus II software through JTAG ELA Resource Utilization ELA uses device resources for implementation ALMs/LEs for ELA megafunction & routing Memory for sample storage LE count is a function of the number of channels & trigger levels Memory block count is a function of number of channels & sample depth Selectable trade-off between depth & number of channels 128K sample depth with 1024 channels not practical – 32,768 M4K blocks Estimated resource usage displayed and update during SignalTap II configuration 6 Feature Overview Feature Benefit Multiple SignalTap II cores Supports multiple clock domains or functional blocks in single device pilation support Add/edit logic analyzer properties without affecting existing design placement & routing Up to 1024 data channels/128K samples per channel View large samples of data Up to 10 trigger conditions Watch for many sequential (or non-sequential) events
