毕业设计（论文）-信号发生器设计与制作 --显示模块的设计与实现.doc

江阴职业技术学院
毕业论文
课题: 信号发生器设计与制作
专题: 显示模块的设计与实现
专业应用电子技术
学生姓名
班级 09应用电子(1)班
学号
指导教师
完成日期 2011年12月18日
摘要
在现代先进的电子系统的前端和后端都将应用到A/D转换器,以改善数字处理技术的性能。在各种A/D转换器中,逐次逼近型A/D转换器是采样率低于5 Msps(每秒百万次采样)的中等至高等分辨率应用的常见结构。由于逐次逼近型A/D转换器具有低功耗、小尺寸的特点,因此有很宽的应用范围。本文设计的8位逐次逼近A/D转换器,采用了以D/A转换器、比较器和带隙基准模块为主体的结构,通过各个模块的优化设计,-、低功耗8位逐次逼近A/D转换器。 D/A转换器模块采用了扩展分辨率的方法,将电阻分压和电容分压相结合,得到了不同缩放方式的DAC组合,扩展D/A转换器分辨率,也提高了转换速度。比较器模块采用了三级比较器通过电容耦合级联的方式来实现,具有高增益的特点,结果所设计的比较器既满足了高速比较的要求,又有效降低了功耗。最后,在A/D转换器中基准电压模块也是一个很重要的组成部分,它直接关系A/D转换器的精度。本文中自主设计的带隙基准电路具有很高的抗电源电压波动和抗温度变化的能力,温度在-50℃-100℃、-。应用Cadence spectre采用CSMC CMOS Nwell工艺库对电路性能进行验证。仿真结果表明,设计的高速比较器、带隙基准电路和D/A转换器满足8位A/D转换的要求。
Abstract
In the front and the end of the advanced electronics systems, analog to digital converters (A/D converters) are applied to improve the performance of the digital processing technique. Of all kinds of A/D converters, essive approximation (SAR)A/D converters are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 mega samples per second (Msps). Because of providing low power consumption as well as a small scale factor, SAR A/D converters have a wide variety of 8-bit medium speed, low power A/D designed in this paper, posed of digital-analog (D/A) converters, comparators ,bandgap and so on. By optimizing the performances of every module, it can operate well from from a signal to power D/A coverter module, in order to extend the resolution of D/A converter, bination of differently scaled DACs is designed. A charge scaling D/A converter with capacitor voltage divider and resistance divider is designed, which extends the resolution of a parallel D/A converter as well as improve speed rate greatly. parator has the character of high gain with the structure of three-stage coupled capacitance, which reduces power consumption as well as satisfies the requirement of high parator