毕业设计（论文）-verilog语言随机存储器的应用探讨与实践.doc

摘要
Verilog是一种用于数字逻辑电路设计的语言。它既是一种行为描述语言,也是一种结构描述语言。也就是说,既可以用电路的功能描述也可用元器件和它们之间的连接来建立所设计电路的verilog模型。本次设计就是以 verilog语言为设计工具,它是在现场可编程门阵列(FPGA)上实现的。软件环境是xilinx的ISE8连接modisim.
本文主要是对可编程逻辑器件—随机存储器的应用探讨与实践,主要讲了与毕设有关的verilog语言,ISE开发环境及随机存储器程序在ISE上的模拟过程。
主要工作有:
;
。

关键词:verilog,现场可编程门阵列,随机存储器
ABSTRACT
Verilog is a language which used in the numeral logic circuit design. It is a kind of behavior
description language. And it is also a kind of structure description language. In other words, the verilog model of the designed circuit can be established by the circuit function description and the
connection ponents. This design took verilog language as the design tool and implemented on FPGA. The software environment is the connection between xilinx ISE6 and modisim.
This paper mainly discussed the programmable ponent (random memory). The verilog language, ISE development environment and random memory programs during the simulation process on ISE which related to graduate design in it.
The main work included:
with the work process and its structure of random memory.
simulation programs with verilog language.
piled analogue results of programs on ISE.
Key words: verilog, FPGA, Random memory
目录
第一章前言 5
,目的: 5
5
5
第二章verilog HDL 6
Verilog语言简介 6
HDL历史 6
7
: 7
7
7
8
Verilog代码编写风格: 8
10
ASIC技术的发展 10
HLD符合目前对电路的两个要求 11
电路设计方法 11
电路设计应该采用的方法 11
Verilog语言的主要能力 11
第三章FPGA简介 13
13
13
13
13
14
15
15
16
16
FPGA前景 17
17
17
18
18
18
18
18
第四章随机存储器 19
19
19
19
: 19
19