[课程设计]EDA大三课程设计.doc

一,课件
今需设计一个十六路彩灯控制器,6种花型循环变化,有清零开关,并且可以选择快慢两种节拍。
根据系统设计要求可知,整个系统共有三个输入信号:控制彩灯节奏快慢的基准时钟信号CLK_IN,系统清零信号CLR,彩灯节奏快慢选择开关CHOSE_KEY;共有16个输出信号LED[15..0],分别用于控制十六路彩灯。
据此,我们可将整个彩灯控制器CDKZQ分为两大部分:时序控制电路SXKZ和显示控制电路XSKZ,。
时序控制电路的VHDL源程序
--
LIBRARY IEEE;
USE ;
USE ;
ENTITY SXKZ IS
PORT(CHOSE_KEY:IN STD_LOGIC;
CLK_IN:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CLK:OUT STD_LOGIC);
END ENTITY SXKZ;
ARCHITECTURE ART OF SXKZ IS
SIGNAL CLLK:STD_LOGIC;
BEGIN
PROCESS(CLK_IN,CLR,CHOSE_KEY) IS
VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF CLR='1' THEN --当CLR='1'时清零,否则正常工作
CLLK<='0';TEMP:="000";
ELSIF RISING_EDGE(CLK_IN) THEN
IF CHOSE_KEY='1' THEN
IF TEMP="011" THEN
TEMP:="000";
CLLK<=NOT CLLK ;
ELSE
TEMP:=TEMP+'1';
END IF;
-- 当CHOSE_KEY='1'时产生基准时钟频率的1/4的时钟信号,否则产生基准时钟
--频率的1/8的时钟信号
ELSE
IF TEMP="111" THEN
TEMP:="000";
CLLK<=NOT CLLK ;
ELSE
TEMP:=TEMP+'1';
END IF;
END IF;
END IF;
END PROCESS;
CLK<=CLLK;
END ARCHITECTURE ART;
显示控制电路的VHDL源程序
--
LIBRARY IEEE;
USE ;
ENTITY XSKZ IS
PORT(CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY XSKZ;
ARCHITECTURE ART OF XSKZ IS
TYPE STATE IS(S0,S1,S2,S2,S4,S5,S6);
SIGNAL CURRENT_STATE:STATE;
SIGNAL FLOWER:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(CLR,CLK) IS
CONSTANT F1:STD_LOGIC_VECTOR(15 DOWNTO 0):="0001000100010001";
CONSTANT F2:STD_LOGIC_VECTOR(15 DOWNTO 0):="1010101010101010";
CONSTANT F2:STD_LOGIC_VECTOR(15 DOWNTO 0):="0011001100110011";
CONSTANT F4:STD_LOGIC_VECTOR(15 DOWNTO 0):="0100100100100100";
CONSTANT F5:STD_LOGIC_VECTOR(15 DOWNTO 0):="10010**********";
CONSTANT F6:STD_LOGIC_VECTOR(15 DOWNTO 0):="1101101101100110";
--六种花型的定义
BEGIN
IF CLR='1' THEN
CURRENT_STATE<=S0;
ELSIF RISING_EDGE(CLK) THEN
CASE CURRENT_STATE IS
WHEN S0=>
FLOWER<="ZZZZZZZZZZZZZZZZ";
CURRENT_STATE<=S1;