静态时序分析基本原理和时序分析模型.ppt

静态时序分析基本原理和时序分析模型 Quartus® II Software Design Series: Timing Analysis
- Timing analysis basics
2
Objectives
Display plete understanding of timing analysis
3
How does timing verification work?
Every device path in design must be analyzed with respect to timing specifications/requirements
Catch timing-related errors faster and easier than gate-level simulation & board testing
Designer must enter timing requirements & exceptions
Used to guide fitter during placement & routing
Used pare against actual results


IN
CLK
OUT
D
Q
CLR
PRE
D
Q
CLR
PRE
combinational delays

CLR
4
Timing Analysis Basics
Launch vs. latch edges
Setup & hold times
Data & clock arrival time
Data required time
Setup & hold slack analysis
I/O analysis
Recovery & removal
Timing models
5
Path & Analysis Types
Three types of Paths:
Clock Paths
Data Path
Asynchronous Paths*
Clock Paths
Async Path
Data Path
Async Path
D
Q
CLR
PRE
D
Q
CLR
PRE
Two types of Analysis:
Synchronous – clock & data paths
Asynchronous* – clock & async paths
*Asynchronous refers to signals feeding the asynchronous control ports of the registers
6
Launch & Latch Edges
CLK
Launch Edge
Latch Edge
Data Valid
DATA
Launch Edge: the edge which “launches” the data from source register
Latch Edge: the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle)
7
Setup & Hold
Setup: The minimum time data signal must be stable
BEFORE clock edge
Hold: The minimum time data signal must be stable
AFTER clock edge
D
Q
CLR
PRE
CLK
Th
Valid
DATA
Tsu
CLK
DATA
Together, the setup time and hold time form a Data Required Window,
the time around a clock edge in which data must be stable.
8
Data Arrival Time
Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
CLK

Tclk1
Data Valid

Tdata
Launch
Edge
Data Valid

Tco
The time for data to arrive at destination register’s D input
REG1
PRE
D