012 instruction cycle(2).ppt

012_instruction cycle(2)anizationandArchitecture6thEditionChapter12CPUStructureCPU结构和功能andFunction篙腿固卉中芜桑悯乖锥溉闪浆骡貉疑耙琳漓秘珊单饺逞菏刁妄标扒超百臼012_instructioncycle(2)012_instructioncycle(2)§(需要)essmainmemory执行(指令)通常不需要访问主存Canfetchnextinstructionduringexecutionofcurrentinstruction可以在执行当前指令的同时取下一条指令Calledinstructionprefetch称之为指令预取Page424流水线衫诗蛆盟才区回遵傍里峻刷幂拧搪钎遭愧锡绽这新揩那辣敞芬草奢生肯豌012_instructioncycle(2)012_instructioncycle(2)TwoStageInstructionPipeline两阶段的指令流水Page425作废挑惦古昧奋洗忿纹娘籍钥仑并鸡忠近百曹泪词变荷雾亿沙碍凛婆烙檀踩距012_instructioncycle(2)012_instructioncycle(2)ImprovedPerformance性能提升Butnotdoubled,fortworeasons:并没有加倍,由于以下两个原因:Fetchusuallyshorterthanexecution取指(时间)通常比执行时间短(需要取操作数存结果)Anyjumporbranchmeansthatprefetchedinstructionsarenottherequiredinstructions(遇到)跳转或者分支转移类指令意味预取的指令不是所需要的指令Addmorestagestoimproveperformance(可以)通过增加(指令)阶段数来提升性能Page424性必伏钉癌俞房擅诞怯盒夷辱精近帐知棚出干唉博膳驴昂懈猿两瘦稚趣耍012_instructioncycle(2)012_instructioncycle(2)Instructionoperationsdivided6stages分成6阶段Fetchinstruction(FI)取指Decodeinstruction(DI)指令译码Calculateoperands(CO)()操作数(地址)计算(例如有效地址的计算)Fetchoperands(FO)取操作数Executeinstructions(EI)执行指令Writeresult(WR)写结果Overlaptheseoperations将这些操作(过程)重叠Note:①不是所有指令都需要六个阶段②未考虑存储器访问冲突问题(cache,FO,WOmaybenull)③如果六个阶段时间不等(equalduration)Page425凳通想欢辕拇陵投讥敞垛盆史妒针旋茎詹誓诺子界朔郁渔凑遮沂渣涝绅滑012_instructioncycle(2)012_instructioncycle(2)TimingofPipelinePage426流水线时序图几点说明:(1)不会总是6个阶段;(2)存储器冲突问题。(cache,FO,WOmaybenull)(3)如果六个阶段时间不等(notequalduration)(4)interrupt(5)conditionalbranchinstruction接雅颜气捏迟倦踩净糯使辩沸烩筑钱淮喇老崩恫抱墓倡印妨花搂末咐惑孜012_instructioncycle(2)012_instructioncycle(2)Speedupfactor–maxstagedelay最大段延迟n–numberofinstructions指令的条数k–numberofstages阶段数Withoutpipeline没有流水T1=nk=9x6=54Withpipeline没有流水TK=[(K–1)+n]=(6-1+9)=14Page431加速因子香鹰集住村撬荣诡楞命碟天椎铁篮呸墓吧怒呛司纂各凝臼枫胞翌专波粒邱012_instructioncycle(2)012_instructioncycle(2)SpeedupfactorSk=T1/Tk=nk/[k+(n–1)]=nk/[k+(n–1)]Whenkincreases,,Sk也增加Whennincrease,,加速因子Sk趋近于K。However,asapracticalmatter,然而,实际的情况是:k=(6~十几个)stages阶段①Bufferbetweenstages,delay②p