eda复习题.doc

:(B)A:采用EEPROM工艺B:采用SRAM工艺C:集成度比PAL和GAL低D:(D)A:高密度B:髙速度C:在系统编程D:(C)(A)IEEE库(B)ASIC库(C)WORK库 (D):(C)(A)USESTD_LOGIC_1164 (B) (C) (D):(B)(A)GENERIC(delay:TIME=20us); (B)GENERIC(delay:TIME:=20us);(C)GENERIC(delayTIME=20us); (D)GENERIC(delay=TIME:=20us);(A):(A)结构体(B)进程(C)函数(D):bit;signalb:bit_vector(1downto0);下面正确的表达式是:(C)(A)b<=a (B)a<=b (C)a<=b(0) (D)a:=b(0),预定义的标准逻辑位数据STD_LOGICE有(D)种逻辑值。:(D)(A)库(B)程序包(C)配置(D)(C):(A)IN (B)OUT (C)BUFFER (D)(C):(A)AND (B)OR (C)NOT (D),b:bit;signaly:bit_vector(1downto0);下面正确的表达式是:(D)(A)y<=a (B)y<=b (C)y<=banda (D)y<=b&:(B)(A):REAL=; (B):REAL:=;(C)REAL=; (D):=;(C):A:常量B:变量C:信号D:,用语句(D)表示检测clock的下升沿。Aclock’EVENTBclock’EVENTANDclock=’lock=’1’Dclock’EVENTANDclock=’0’:(C)。、元件、常数、.,最高优先级的运算操作符是(C)。.*,其变量更新是(A)。;;;。19. 在一个VHDL设计中idata是一个信号,数据类型为std_logic_vector,试指出下面(D)赋值语句是错误的。<=“00001111”<=B”0000_1111”<=X”AB”<=B”21”:(C)。 (C)。Ⅱ的(A)命令,可以在底层设计时创建元件的图形符号。,用语句(B)表示检测到时钟clk的上升沿。’(clk)=‘0’=’1’(B)。A.=B.<=C.:=D.=:=“6”,b=“E”,则以下程序执行后,c的值为(B)。entitylogicisport(a,b:instd_logic_vector(3downto0);c:outstd_logic_vector(7downto0));endlogic;architectureaoflogicisbeginc(0)<=a(0);c(2downto1)<=a(2downto1)andb(2downto1);c(3)<='1'xorb(3);c(7downto4)<="1111"when(a(2)=b(2))else"0000";enda;A.“F8”B.“F