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Voltage Reference Design for Precision essive-Approximation ADCs By Alan Walsh The overall precision ofa high-resolution, essive-approximation ADC depends on the accuracy, stability, and drive capability of its voltage reference. The switched capacitors on the ADC ’s reference input present a dynamic load, so the reference circuit must be able to handle time- and throughput-dependent currents. Some ADCs integrate the reference and reference buffer on chip, but these may not be optimal in terms of power or performance — and the best performance can usually be achieved with an external reference circuit. This article looks at the challenges and requirements involved with the reference circuit design. Reference Input A simplified schematic ofa essive-approximation ADC is shown in Figure 1. During the sampling interval, the capacitive DAC is connected to the ADC input, and a charge proportional to the input voltage is stored on its capacitors. When the conversion starts, the DAC is disconnected from the input. The conversion algorithm essively switches each bit to the reference or ground. Charge redistribution on the capacitors causes current to be drawn from or sunk by the reference. This dynamic current load isa function of both the ADC throughput rate and the internal clock that controls the bit trials. The most significant bits (MSBs) hold the most charge and require the most c