edaveriloghdl十二分频器程序.doc十二分频器程序 :
module cnt12(reset,clkin,clkout,qout); input reset,clkin;
output clkout,qout;
reg clkout;
reg[4:0] qout;
always @(posedge clkin)
begin
if(!reset) qout<=0;
else if(qout<11) qout<=qout+1;
else qout<=0;
end
always @(posedge clkin)
begin
if(!reset) clkout<=0;
else if(qout==11) clkout<=1;
else clkout<=0;
end
endmodule
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