EDA第五讲优化和时序分析.ppt

EDA 技术实用教程
第 五 讲
优化和时序分析
资源优化
资源共享
【例11-1】
LIBRARY ieee;
USE ;
USE ;
USE ;
ENTITY multmux IS
PORT (A0, A1，B : IN std_logic_vector(3 downto 0);
sel : IN std_logic;
Result : OUT std_logic_vector(7 downto 0));
END multmux;
ARCHITECTURE rtl OF multmux IS
BEGIN
process(A0,A1,B,sel)
begin
if(sel = '0') then Result <= A0 * B;
else Result <= A1 * B;
end if;
end process;
END rtl;
资源优化
资源共享
图11-1 先乘后选择的设计方法RTL结构
资源优化
资源共享
图11-2 先选择后乘设计方法RTL结构
资源优化
资源共享
【例11-2】
ARCHITECTURE rtl OF muxmult IS
signal temp : std_logic_vector(3 downto 0);
BEGIN
process(A0,A1,B,sel)
begin
if(sel = '0') then temp <= A0; else temp <= A1;
end if;
result <= temp * B;
end process;
END rtl;
资源优化
资源共享
图11-3 资源共享反例
资源优化
逻辑优化
【例11-3】
LIBRARY ieee;
USE ;
use ;
use ;
ENTITY mult1 IS
PORT(clk : in std_logic;
ma : In std_logic_vector(11 downto 0);
mc : out std_logic_vector(23 downto 0));
END mult1;
ARCHITECTURE rtl OF mult1 IS
signal ta，tb : std_logic_vector(11 downto 0);
BEGIN
process(clk) begin
if(clk'event and clk = '1') then
ta <= ma; tb <= "1"; mc <= ta * tb;
end if;
end process;
END rtl;
资源优化
逻辑优化
【例11-4】
LIBRARY ieee;
USE ;
use ;
use ;
ENTITY mult2 IS
PORT(clk : in std_logic;
ma : In std_logic_vector(11 downto 0);
mc : out std_logic_vector(23 downto 0));
END mult2;
ARCHITECTURE rtl OF mult2 IS
signal ta : std_logic_vector(11 downto 0);
constant tb : std_logic_vector(11 downto 0) := "1";
BEGIN
process(clk) begin
if(clk'event and clk = '1