流水灯等.docx

流水灯 LIBRARY IEEE; USE ; USE ; USE ; ENTITY lsd IS PORT ( CLK : IN STD_LOGIC; -- 移位时钟 DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8 位移位显示码 END lsd; ARCHITECTURE behav OF lsd IS SIGNAL SLIP : STD_LOGIC_VECTOR(24 DOWNTO 0); SIGNAL COUNT : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL M: STD_LOGIC; BEGIN PROCESS (CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN SLIP<=SLIP+1; END IF; M<=SLIP(24); END PROCESS; PROCESS(M) BEGIN IF M'EVENT AND M='1' THEN COUNT<=COUNT+1; END IF; CASE COUNT IS WHEN "000"=> DOUT<="00000001"; WHEN "001"=> DOUT<="00000010"; WHEN "010"=> DOUT<="00000100"; WHEN "011"=> DOUT<="00001000"; WHEN "100"=> DOUT<="00010000"; WHEN "101"=> DOUT<="00100000"; WHEN "110"=> DOUT<="01000000"; WHEN "111"=> DOUT<="10000000"; WHEN OTHERS=>DOUT<="00000001"; END CASE; END PROCESS; END behav; 带进位输入、输出的 8 位全加器端口: A、B 为加数, CIN 为进位输入, S 为加和, COUT 为进位输出 LIBRARY IEEE; USE ; ENTITY ADDER8 IS PORT (A, B: IN STD_LOGIC_VECTOR (7 DOWNTO 0); CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC; S: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ADDER8; ARCHITECTURE ONE OF ADDER8 IS SIGNAL TS: STD_LOGIC_VECTOR (8 DOWNTO 0); BEGIN TS <=(?0?& A)+(?0?& B)+ CIN; S <= TS(7 DOWNTO 0); COUT <= TS(8); END ONE; LIBRARY IEEE; USE ; ENTITY TRI_STATE IS PORT ( E,A: IN STD_LOGIC; Y: INOUT STD_LOGIC; B: OUT STD_LOGIC); END TRI_STATE; ARCHITECTURE BEHAV OF TRI_STATE IS BEGIN PROCESS (E, A, Y) BEGIN IFE= '0' THEN B <= Y;Y <= 'Z'; ELSE B <= 'Z'; Y <= A; END IF; END PROCESS; END BEHAV; C ount60 module count60(clk,out,reset,cin,ocom); output[3:0] ocom; output[7:0] out; input cin,clk,reset; reg[7:0] out_s; reg[7:0] out; reg[3:0] ocom; reg[3:0] in_out; reg select,clk_m,clk_n; integer count_clk,count_cp; always @(posedge clk) if (count_cp == 50000) begin count_cp = 0; clk_n = ~clk_n; end else count_cp = count_cp + 1; always @(posedge clk) if (count_clk == 12500000) begin count_clk = 0; clk_m = ~clk_m; end else count_clk