兼容51指令的8位MCU IP CORE开发.docx

兼容51指令的8位MCU I P CORE开发
摘要
当前，在微电子领域正在发生一场前所未有的变革．这场变革是 由片上系统(SOC)技术的研究开展引起的，从技术层面看SOC技术是超 大规模集成电路开展的必然趋势和产物th the MCS一5 1 family microcontroller instruction set．It consists of an 8-bit CPU．two 1 6．bit timers／counters，a UART，four groups of 8一bit parallel ports and 256 bytes of RAM．Harvard architecture，in which the data bus iS separated from the program bus，is adopted，therefore its exterior RAM and ROM call be extended to 64 KB．
In the IP core，the ALU which executes arithmetic and logic operatiOIlS iS composed of the pure combination logic circuits．It includes add／sub operation module，multiplication operation module，division operation module，decimal
adjustment operation module，logic operation module and multi—mux module and
logic instructions．The new PLA hard—wired logic instead of micro—programe control logic in the controller iS adopted．In the instruction FSM，a new instruction sequence
and a new implementation mode are utilized，and the combinational logic is separated from the sequential logic to improve its execution efficiency．
A1l the modules in the IP core are described by the VHDL language which has
UI
better transplantation．An R，I’L functional simulation and a synthesis test of the individual module and the integrated core are made by the MODELSIM software in MENTOR company and DC software in SYNOPSYS company．A hardware
validation is performed by test on the XILLINX’S Virtex-4 SX simulation board．
111e software simulation and the hardware test show that the maximum clock frequency Can be as high as 25．36 MHz and the chip area consumed via the synthesis is moderate．Therefore，it Can be completely integrated as a controller core in the SoC
chips．
KEY WORDS：MCU；IP；VHDL；SOC
IV
广西大学学位论文原创性声明和使用授权说明
原创性声明
本人声明：所呈交的学位论文是在导师指导下完成的，研究工作所取得的 成果和相关知识产权属广西大学所有，本人保证不以其它单位为第一署名单位 发表或使用本论文的研究内容。除已注明局部外，论文中不包含其他人已经发