EDA实验报告.doc

(原理图)
时序仿真图:
(VHDL语言)
LIBRARY IEEE;
USE ;
USE ;
ENTITY counter32_2 IS
PORT( en : IN STD_LOGIC;
clr : IN STD_LOGIC;
clk : IN STD_LOGIC;
q : BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);
c : OUT STD_LOGIC);
END counter32_2;
ARCHITECTURE a OF counter32_2 IS
BEGIN
PROCESS (clk,clr)
BEGIN
IF(clr ='0') THEN
q<=(OTHERS=>'0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en='1') THEN
IF (q="11111") THEN
q<="000000";
ELSE
q<=q+'1';
END IF;
END IF;
END IF;
c<=q(0) AND q(1) AND q(2)AND q(3)AND q(4);
END PROCESS;
END a ;
时序仿真图:

LIBRARY IEEE;
USE ;
ENTITY coder83 IS
PORT(I0,I1,I2,I3,I4,I5,I6,I7: IN STD_LOGIC;
A0,A1,A2: OUT STD_LOGIC);
END coder83;
ARCHITECTURE behave OF coder83 IS
BEGIN
A2 <= I4 OR I5 OR I6 OR I7;
A1 <= I2 OR I3 OR I6 OR I7;
A0 <= I1 OR I3 OR I5 OR I7;
END behave;
时序仿真图:

LIBRARY IEEE;
USE ;
ENTITY prioritycoder83_2 IS
PORT(I7,I6,I5,I4,I3,I2,I1,I0 : IN STD_LOGIC;
EI:IN STD_LOGIC;
A2,A1,A0: OUT STD_LOGIC;
GS,EO:OUT STD_LOGIC);
END prioritycoder83_2;
ARCHITECTURE behave OF prioritycoder83_2 IS
BEGIN
A2 <= EI OR (I7 AND I6 AND I5 AND I4);
A1 <= EI OR (I7 AND I6 AND I3 AND I2) OR (I7 AND I6 AND NOT I5)
OR (I7 AND I6 AND NOT I4) ;
A0 <= EI OR (I7 AND NOT I6) OR (I7 AND I5 AND NOT I4)
OR (I7 AND I5 AND I3 AND I1) OR (I7 AND I5 AND I3 AND NOT I2);
GS <= EI OR (I7 AND I6 AND I5 AND I4 AND I3 AND I2 AND I1 AND I0);
EO <= EI OR NOT(I7 AND I6 AND I5) AND I4 AND I3 AND I2 AND I1 AND I0);
END behave;
仿真图如下:

3译码器
LIBRARY IEEE;
USE ;
ENTITY decoder38 IS
PORT(G1,G2A,G2B: IN STD_LOGIC;
A: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END decoder38;
ARCHITECTURE dataflow OF decoder38 IS
BEGIN
PROCESS (G1,G2A,G2B,A)
BEGIN
IF(G1='1' AND G2A='0' AND G2B='0')THEN
CASE A IS
WHEN "000" => Y <="111