High Level Design For High Speed FPGA Devices
Man. Ng mcn99
Department puting
Imperial College
June 13, 2002
Acknowledgement
Before starting the report, I would like to thank the following people for helping me throughout the project. Without their help, it would be impossible for me to finish the project:
I would like to thank my supervisor Dr. Wayne Luk for giving me a lot of useful advices and encouragement throughout the project. He also guided me towards the problems I should focus on during the implementation. I would like to thank Professor Yang for letting me to implement his gel-image processing algorithm on hardware. He also gave me references and example sources to understand the theories underneath. And I would like to thank for his teaching in his excellent multimedia course. The course conveyed many useful concepts for me to understand the gel image processing I would like to thank Altaf and Shay. They are two research students who helped me a lot throughout the implementation of the application.
Abstract
In the project, I have discovered a systematic approach for high-level hardware design. With this approach, I essfully implemented the sophisticated gel image processing on high speed hardware. In the report, I will also introduced a new technique which can automate the process of high level hardware performance optimization by rearranging the code sequence so that the it can be run at minimum number of clock cycles. The report will be split into 4 Chapters:
Chapter 1 is Introduction. It includes the background, all the related works and my contribution to the project.
Chapter 2 is Optimization. In this chapter, I will focus on the techniques for optimization. I will also demonstrate some techniques which can automate the optimization process.
Chapter 3 is Hardware Development. In this chapter, I will generalize the steps of converting a software programme into hardware. These include several techniques which can improve the performan
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