第十三讲 VHDL语言语言组合逻辑电路设计.ppt

在系统可编程技术
第13讲
VHDL语言语言组合逻辑电路设计
一、逻辑门电路设计
例1:用数据流描述方式设计一个4输入“与或非”逻辑门
LIBRARY IEEE;
USE ;
ENTITY yhf4 IS
PORT(A,B,C,D: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END yhf4;
ARCHITECTURE data_flow OF yhf4 IS
BEGIN
Y<=NOT((A AND B) OR (C AND D));
END data_flow;
请画出电路图
例2:设计一双向8位总线驱动器
LIBRARY IEEE;
USE ;
ENTITY qd8 IS
PORT( A,B: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EN,DIR:IN STD_LOGIC);
END qd8;
ARCHITECTURE behavior OF qd8 IS
SIGNAL AOUT,BOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
AB:PROCESS(A,EN,DIR)
IF ((EN=‘0’) AND (DIR=‘1’) THEN
BOUT<=A;
ELSE
BOUT<=“ZZZZZZZZ”;
END IF;
B<=BOUT;
END PROCESS AB;
为什么定义信号?
BA:PROCESS(B,EN,DIR)
IF ((EN=‘0’) AND (DIR=‘0’) THEN
AOUT<=B;
ELSE
AOUT<=“ZZZZZZZZ”;
END IF;
END PROCESS BA;
A<=AOUT
END behavior;
例2:设计一双向8位总线驱动器
二
编码器设计
例1:设计8-3优先权编码器
LIBRARY IEEE;
USE ;
ENTITY bmq83 IS
PORT( D: IN STD_LOGIC_VECOR(7 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END bmq83;
ARCHITECTURE behavior OF bmq83 IS
BEGIN
PROCESS(D)
BEGIN
IF D(7)=‘0’ THEN Y<=“000”;
ELSIF D(6)=‘0’ THEN Y<=“001”;
ELSIF D(5)=‘0’ THEN Y<=“010”;
ELSIF D(4)=‘0’ THEN Y<=“011”;
ELSIF D(3)=‘0’ THEN Y<=“100”;
ELSIF D(2)=‘0’ THEN Y<=“101”;
ELSIF D(1)=‘0’ THEN Y<=“110”;
ELSIF D(0)=‘0’ THEN Y<=“111”;
ELS Y<=“XXX”;
END PROCESS;
END behavior;
该描述具有优先级
三译码器设计
例1:设计3-8线译码器
LIBRARY IEEE;
USE ;
ENTITY ymq83 IS
PORT(A,B,C: IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ymq83;
请注意
数据类型的声明
ARCHITECTURE behavior OF ymq83 IS
SIGNAL INDATA:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
INDATA<=C&B&A;
PROCESS(INDATA)
BEGIN
CASE INDATA IS
WHEN “000”=> Y<=“11111110”;
WHEN “001”=> Y<=“11111101”;
WHEN “010”=> Y<=“11111011”;
WHEN “011”=> Y<=“11110111”;
WHEN “100”=> Y<=“11101111”;
WHEN “101”=> Y<=“11011111”;
WHEN “110”=> Y<=“10111111”;
WHEN “111”=> Y<=“01111111”;
WHEN OTHERS => Y<=“XXXXXXXX”;
END CASE;
END PROCESS;
END behavior;
该描述
不具有优先级
例1:设计3-8线译码器
译码器设计
四、运