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Adding Your Own IP to the OPB Bus
Objectives
pleting this module, you will be able to:
Understand basic OPB bus transactions
Differentiate between free and evaluation-based IP delivered in EDK
Identify the requirements for integrating your IP
List the steps involved in importing peripherals when using the wizard
List the limitations of creating peripherals with the wizard
Outline
OPB Bus
OPB User Core Templates
XPS Directory Structure
File Creation: MPD, PAO, BBD
IP Delivery in EDK
Creating/Importing Peripheral Wizard
Overview
The peripherals are connected to the microprocessor by using the data and address buses
Xilinx has implemented IBM's CoreConnect bus architecture
On-chip Peripheral Bus (OPB) version of the CoreConnect architecture is designed for easy connection of on-chip peripheral devices
Any custom peripheral that connects to the OPB bus must do the following:
Meet the principles of the OPB protocol
Meet the requirements of the Platform Generator
This allows you to take advantage of the simple automated flow that generates the system-level architecture
Features
Platform Generator supports the following features for OPB peripherals, and it is a subset of the OPB features
Fully synchronous single-clock edge
32-bit address bus, 32-bit data bus
Single-cycle transfer of data between the OPB master and the OPB slave
Supports master byte enables
Supports slave timeout suppress
Supports slave retry
No three-state drivers required
Note that the dynamic bus sizing feature is not supported in OPB
Features
MicroBlaze embedded system
Features
IBM PowerPC embedded system
Physical Implementation
The OPB bus architecture () allows for the addition of peripherals to the system, without changing the existing I/O on either the OPB arbiter or the other existing peripherals
Interface Signals
Platform Generator does the following
Counts the number of devices attached to the OPB
Instantiates opb_v20
Connects the address bus, data buses,