约翰逊计数器.ppt

约翰逊计数器约翰逊计数器————Verilog语言moduleJohnson_4_1s(clk,rest,Q);//主模块,四个D触发器和一inputclk;//个秒脉冲模块组成inputrest;output[3:0]Q;wire[3:0]d;wirea;assignd[0]=Q[1];assignd[1]=Q[2];assignd[2]=Q[3];assignd[3]=~Q[0]|~Q[1]&Q[2];D_FFdff0(rest,a,d[0],Q[0]);D_FFdff1(rest,a,d[1],Q[1]);D_FFdff2(rest,a,d[2],Q[2]);D_FFdff3(rest,a,d[3],Q[3]);cp_1scp1(rest,clk,a);endmodulemoduleD_FF(rest,clk,d,q);//D触发器模块inputrest;inputclk;inputd;outputq;regq;always@(posedgerestorposedgeclk)if(rest==1'b1)beginq<=1'b0;endelsebeginq<=d;endendmodulemodulecp_1s(rest,clk,a);//秒脉冲模块,输出a为一秒的脉冲inputrest;inputclk;outputrega; reg[25:0]q;always@(posedgeclkorposedgerest)beginif(rest==1) begin q<=0; a<=0; endelseif(q==24999999) begin q<=0; a<=~a; endelse q<=q+1; endendmodule