EDA数字秒表课程设计.doc

程序:(1)时基分频模块的VHDL源程序()LIBRARYIEEE;;;ENTITYCB10ISPORT(CLK:INSTD_LOGIC;——输入时钟信号CO:OUTSTD_LOGIC);——分频输出信号ENDCB10;——实体描述ARCHITECTUREARTOFCB10IS——结构体描述SIGNALCOUNT:STD_LOGIC_VECTOR(3DOWNTO0);——硬件系统的基本数据对象BEGINPROCESS(CLK)——进程敏感信号BEGINIFRISING_EDGE(CLK)THENIFCOUNT="1001"THENCOUNT<="0000";CO<='1';ELSECOUNT<=COUNT+1;CO<='0';ENDIF;ENDIF;ENDPROCESS;ENDART;(2)控制模块的VHDL源程序()LIBRARYIEEE;;;ENTITYCTRLISPORT(CLR,CLK,SP:INSTD_LOGIC;EN:OUTSTD_LOGIC);——CLR:清零信号CLK:脉冲输入端SP:计数输入端EN:输出端END;ARCHITECTUREBEHAVEOFCTRLISCONSTANTS0:STD_LOGIC_VECTOR(1DOWNTO0):="00";CONSTANTS1:STD_LOGIC_VECTOR(1DOWNTO0):="01";CONSTANTS2:STD_LOGIC_VECTOR(1DOWNTO0):="10";CONSTANTS3:STD_LOGIC_VECTOR(1DOWNTO0):="11";TYPESTATESIS(S0,S1,S2,S3);——表达四个状态的位矢量SIGNALCURRENT_STATE,NEXT_STATE:STATES;:PROCESS(SP,CURRENT_STATE)——决定转换状态的进程BEGINCASECURRENT_STATEISWHENS0=>EN<='0';——选中状态为S0、EN='0'IFSP='1'THENNEXT_STATE<=S1;ELSENEXT_STATE<=S0;ENDIF;WHENS1=>EN<='1';——选中状态为S1、EN='1'IFSP='1'THENNEXT_STATE<=S1;ELSENEXT_STATE<=S2;ENDIF;WHENS2=>EN<='1';——选中状态为S2、EN='1'IFSP='1'THENNEXT_STATE<=S3;ELSENEXT_STATE<=S2;ENDIF;WHENS3=>EN<='0';——选中状态为S3、EN='0'IFSP='1'THENNEXT_STATE<=S3;ELSENEXT_STATE<=S0;ENDIF;ENDCASE;ENDPROCESS;SYNCH:PROCESS(CLK)——时序进程BEGINIFCLR='1'THENCURRENT_STATE<=S0;ELSIFCLK'EVENTANDCLK='1'THENCURRENT_STATE<=NEX