S3C44B0中文手册.docx

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介 绍
三星的S3c44B0X 16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方 案。
S3C44B0X 提供以下配置： ARM7TDMI 内核带有 8Kcache ;可选的 internal SRAM;LCD Controlled 最大支持 256色 STN,使用 LCD 专用 DMA) ; 2-ch UART with handshake(, 16-byte FIFO) / 1-ch SIO ; 2-ch general DMAs / 2-ch peripheral DMAs with external request pins; External memory controller (chip select logic, FP/ EDO/SDRAM controller) ; 5-ch PWM timers & 1-ch internal timer ; Watch Dog Timer ; 71 general purpose I/O ports / 8-ch external interrupt source ; RTC with calendar function ; 8-ch 10-bit ADC; 1-ch multi-master IIC-BUS controller ; 1-ch IIS-BUS controller ; Sync. SIO interface and On-chip clock generator with PLL.。
S3c44B0X采用一种新的三星 ARM CPU嵌入总线结构-SAMBA2 ,最大达66MHZ。 电源管理支持：Normal, Slow, Idle, and Stop mode 。
系统管理功能：
1 Little/Big endian support.
2 Address space: 32Mbytes per each bank. (Total 256Mbyte)
3 Supports programmable 8/16/32-bit data bus width for each bank.
4 Fixed bank start address and programmable bank size for 7 banks. memory banks.
-6 memory banks for ROM, SRAM etc.
-2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM)
6. Fully Programmable access cycles for all memory banks.
Supports external wait signal to expend the bus cycle.
Supports self-refresh mode in DRAM/SDRAM for power-down.
Supports asymmetric/symmetric address of DRAM.
Cache和内部存储器功能：
? 4-way set associative ID(Unified)-cache with 8 Kbyte.
? The 0/4/8 Kbytes internal SRAM using unused cache memory.
? Pseudo LRU(Least Recently Used) Replace Algorithm.
? Write through policy to maintain the coherence between main memory and cache content.
? Write buffer with four depth.
? Request data first fill technique when cache miss occurs. 时钟和电源管理
? Low power
? The on-chip PLL makes the clock for operating MCU at maximum 66MHz.
? Clock can be fed selectively to each function block by software.
? Power mode: Normal, Slow, Idle and Stop mode.
Normal mode: Normal operating mode. Slow mode: Low frequency clock without P