eda习题答案.doc

21 mux
2
(1)使用 if... .then 语句
process(sO
/ si
,a, begin
if sO
=
•of
and si = * 01 then
y
<=
a；
elsif
sO
=
119 and si = 101 then
y
<=
b;
elsif
sO
=
• 01 and si = * 11 then
y
<=
c;
:*T"；
:士：
else
y
<=
d;
end if;
end process;
(2)、使用case语句
architecture hdlarch of mux41 is
signal stmp : std_logic_vector(1 downto 0); hegin
stmp <= si
& sO;
：..卜：
士
process(s0#
S1 / a./ D /
c,
d) begin
case strno is
:.干.： 吐.：
when
•»oon =>
y
<=a;
when
H01n =>
y
<=b;
when
•»10n =>
y
<=c;
when
others
=>
y <= d;
end case;
end process;
architecture hdlarch of MUXK is
signal tmp : sta^logic; cegin
process(sO# m3) begin
if sO = 101 then
tmp <= a2;
else
tmp <= a3;
:干：
.- 吐•：
end if;
end process;
process(si,al,tmp) begin
if si = 10 * then
outy <= al;
else
outy <= tmp;
end if;
end process;
end hdlarch;
4、 (1)
先设计一个半减器:
x y
00
01
10
11
diff
0
1
1
0
s_out
0
1
0
0
library ieee;
use ieee ・ std_logic_ll64 ・ all;
entity h_suber is
port (
x#y : in std^logic;
diff,s_out : out std^logic
)；
end entity ;
architecture hdlarch of h^suber is cegin process(xf y) begin
diff <= x xor y; s_out <= (not x) and y;
end process;
end hdlarch;
(2) 1位全减器的VHDL
LIBRARY ieee;
USE ieee ・ sta_logic_1164 ・ all;
ENTITY suber IS
port (
xzy : IN STD_LOGIC; sub_in : IN STD_LOGIC; diffr