PLL论文——A Spur-Frequency-Boosting PLL With a ?74 dBc.pdf

2104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 9, SEPTEMBER 2013 A Spur-Frequency-Boosting PLL With a ?74 dBc Reference-Spur Suppression in 90 nm Digital CMOS Mohamed M. Elsayed , Member, IEEE , Mohammed Abdul-Latif, and Edgar Sánchez-Sinencio , Life Fellow, IEEE Abstract— An architectural solution for designing a low-refer- ence-spur PLL is proposed. Aspur-frequency boosting block is in- serted between the phase-frequency detector and the charge pump to boost the charge pump input frequency. Hence, the spur at the reference frequency is eliminated and is frequency-boosted to a higher frequency, , at which the PLL gain is much less resulting in greater suppression. Quantitative analysis of the charge pump spurs is presented to clarify the different tradeoffs affecting the output spurs level. The proposed technique breaks the classical trade off between the different PLLparameters. It adds a degree of freedom in PLL design to reduce the reference spur level without reducing neither the loop bandwidth nor the voltage-controlled os- cillator’s gain (K ). A GHz PLL prototype is fabricated using UMC 90 nm digital CMOS technology. A ?74 dBc refer- ence-spur suppression is measured along with a (K / ω)ratio of and a ( ω/ ω) ratio of 1/20. The proposed architec- ture provides additional spur suppression of 30 pared to a conventional PLL and, to the best of the authors’ knowledge, this PLL provides the best normalized reference-spur rejection in lit- erature. The prototype occupies mm2. Index Terms— Phase locked loop, PLL, r eference spurs, spurs, frequency synthesizers, time-to- voltage converters, voltage-to-time converters, low spurs, spur boosting, spur regeneration. I. I NTRODUCTION P HASE-LOCKED LOOPs (PLLs) play an important role in munication systems. Integer PLLs have numerous applications especially in wireline applications (elec- trical or optical). This market is a solid market and is seeing a growing trend due to the evolution of puti