采用嵌入微控制器的在系统编程.pdf

XAPP058 () June 25, 2004-800-255-7778? 2001-2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This bination of features allows designers to make significant changes and yet keep the original device pinouts, thus, eliminating the need to re-tool PC boards. By using an embedded controller to program these CPLDs and FPGAs from an on-board RAM or EPROM, designers can easily upgrade, modify, and test designs, even in the FamiliesXC9500, XC9500XL, XC9500XV, XC4000, XC18V00, CoolRunner?, Spartan?, Virtex?IntroductionThe Xilinx CPLD and FPGA bine superior performance with an advanced architecture to create new design opportunities that were previously impossible. bination of in-system programmability, reliable pin locking, and JTAG test capability gives the following important benefits:? Reduces device handling costs and time to market? Saves the expense of laying out new PC boards? Allows remote maintenance, modification, and testing? Increases the life span and functionality of products? Enables unique, customer-specific featuresThe ISP controller shown in Figure 1 can help designers achieve these unprecedented benefits by providing a simple means for automatically programming Xilinx CPLDs and FPGAs from design information stored in EPROM. This design is easily modified for remote downloading applications and the included C-code can piled for any create device programming files, Xilinx provides the JTAG ProgrammerTM software that automatically reads standard JEDEC/BIT/MCS/EXO device programming files and converts them to