数字时钟设计--EDA课程设计.doc

EDA课程设计
数字时钟设计
姓名:
学号:
专业:电子信息工程
班级:
指导教师:
2012年 11月 8日
目录
一、前言·························································2
EDA简介··················································2
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Verilog HDL简介············································2
题目分析·····················································2
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总体RTL电路图
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三、各模块分析···················································5
四、仿真测试····················································13
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五、心得体会····················································14
六、参考文献····················································14
七、评分表······················································15
一、前言
EDA简介
EDA是电子设计自动化(Electronic Design Automation)的缩写,在20世纪90年代初从计算机辅助设计(CAD)、计算机辅助制造(CAM)、计算机辅助测试(CAT)和计算机辅助工程(CAE)的概念发展而来的。EDA技术就是以计算机为工具,设计者在EDA软件平台上,用硬件描述语言HDL完成设计文件,然后由计算机自动地完成逻辑编译、化简、分割、综合、优化、布局、布线和仿真,直至对于特定目标芯片的适配编译、逻辑映射和编程下载等工作。

数字钟亦称数显钟(数字显示钟),是一种用数字电路技术实现时、分、秒计时的装置,与机械时钟相比,直观性为其主要显著特点,且因非机械驱动,具有更长的使用寿命,相较石英钟的石英机芯驱动,更具准确性。数字钟已成为人们日常生活中必不可少的必需品,广泛用于个人家庭以及车站、码头、剧院、办公室等公共场所,给人们的生活、学习、工作、娱乐带来极大地方便。相对于其他时钟类型,它的特点可归结为“两强一弱”:比机械钟强在观时显著,比石英钟强在走时准确,但是它的弱点为显时较为单调。
Verilog HDL简介
Verilog HDL是一种硬件描述语言(HDL:Hardware Discription Language),是一种以文本形式来描述数字系统硬件的结构和行为的语言,用它可以表示逻辑电路图、逻辑表达式,还可以表示数字逻辑系统所完成的逻辑功能。 Verilog HDL和VHDL是目前世界上最流行的两种硬件描述语言,都是在20世纪80年代中期开发出来的。前者由Gateway Design Automation公司(该公司于1989年被Cadence公司收购)开发。两种HDL均为IEEE标准。
二、题目分析
用Verilog设计一个多功能的数字钟,具有下述功能:
(1)、计时功能:包括时,分,秒的计时;
(2)、定时与闹钟功能:能在设定的时间发出闹铃声;
(3)、校时功能:对时、分和秒能手动调整以校准时间;
(4)、整点报时功能:每逢整点,产生“滴滴滴滴-嘟”四短一长的报时音。

1)时、分、秒计时器及整点报时功能
时计时器为一个24进制计数器,分、秒计时器均为60进制计数器。当秒计时器接受到一个秒脉冲时,秒计数器开始从1计数到6