基于斜线划分的平面化零时滞时钟布线算法分析.docx

摘要
高性能特别是高速、低功耗的集成电路是当今半导体产业发展的热点,而时钟分布电路的设计是高性能电路设计中最具有挑战性最重要的部分之一。该问题被1999年ACM物理设计国际会议(ISPD)列为本世纪集成电路物理设计的十大前沿问题之~。现在芯片的集成度已经达到几千万晶体管和七层铜互连的量级,而时钟频率也高达几个GHz。随着信号频率的上升,连线上的电容电感效应越来越突出,线上延时的影响日益增大。对于高频时钟电路来说,一方面,如果时钟信号不能在指定时刻传送到接收端点,电路的时序就会就被打乱,导致功能失常:另一方面,如果接收到的时钟信号不是一个完整的信号,电路就不能被有效驱动。因此,时钟分布电路的物理综合是学术界和工业界迫切需要研究的课题。我们的目标是在单层平面上实现时钟分布电路的布线,在插入尽可能少的缓冲器的前提下,使得GHz的高频时钟信号可以完整地、无偏差地传输到每一个接收端点。
,提出了基于斜线划分的平面化零时滞时钟布线算法,新算法有很好的普适性和灵活性。具体工作有:1)用斜线进行平衡划分,得到在欧几里德平面上满足平面化的时钟树; 2)把满足欧几里德平面化的时钟树转换成满足曼哈顿平面化的切割线二叉树;3) 把切割线看成虚拟通道,进行粗略布线t 4)在虚拟通道内进行连线调整,把重叠的连线错开。在此基础上,。我们的方法能够处理周丽丽的方法无法解决的一些问题,获得性能更好的时钟树,并且细化了平面化时钟布线的过程,将各步骤模块化,各模块子算法可以灵活选取。
关键词:时钟树 综合GHz零时滞 平面化布线
Abstract
High performance circuits especially high speed and low power ones have been the hot spot of the semiconductor of the clock distribute circuits have been the most challenging and important part of the hJ【gh performance circuits problem has been known as one of the top ten advanced problems On the ISPD conference in ,the IC technology has thousands of transistors and seven—layer Cu the signal frequency rising,the effect of the conductance and inductance on the intercormection es more and more important and the delay of the interconnection takes more part than the delay of the
one hand,if the signals cannot arrive at the clock sinks Oil time,the circuit’s time order will be disturbed and the circults carl’t the other iS also
all important problem for the high frequency circuits that the signal can arrive at the sinks the clock distribute circuit synthesis problem is the great needed project both in research field and this application background,our goal is to realize the clock distribute circuits design on planar and the GHz frequency signal can arrive at the sinks without skew and safely,at the same time,the number of the inserted buffers