EDA数字秒表课程设计论文.doc

程序:
(1)时基分频模块的VHDL源程序()
LIBRARY IEEE;
USE ;
USE ;
ENTITY CB10 IS
PORT(CLK:IN STD_LOGIC; ——输入时钟信号
CO:OUT STD_LOGIC); ——分频输出信号
END CB10; ——实体描述
ARCHITECTURE ART OF CB10 IS ——结构体描述
SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
——硬件系统的基本数据对象
BEGIN
PROCESS(CLK) ——进程敏感信号
BEGIN
IF RISING_EDGE(CLK)THEN
IF COUNT="1001"THEN
COUNT<="0000";
CO<='1';
ELSE
COUNT<=COUNT+1;
CO<='0';
END IF;
END IF;
END PROCESS;
END ART;
(2)控制模块的VHDL源程序()

LIBRARY IEEE;
USE ;
USE ;
ENTITY CTRL IS
PORT(CLR,CLK,SP:IN STD_LOGIC;
EN:OUT STD_LOGIC); ——CLR:清零信号
CLK:脉冲输入端
SP:计数输入端
EN :输出端
END;
ARCHITECTURE BEHAVE OF CTRL IS
CONSTANT S0:STD_LOGIC_VECTOR(1 DOWNTO 0):="00";
CONSTANT S1:STD_LOGIC_VECTOR(1 DOWNTO 0):="01";
CONSTANT S2:STD_LOGIC_VECTOR(1 DOWNTO 0):="10";
CONSTANT S3:STD_LOGIC_VECTOR(1 DOWNTO 0):="11";
TYPE STATES IS(S0,S1,S2,S3); ——表达四个状态的位矢量
SIGNAL CURRENT_STATE,NEXT_STATE:STATES;
BEGIN
COM:PROCESS(SP,CURRENT_STATE) ——决定转换状态的进程
BEGIN
CASE CURRENT_STATE IS
WHEN S0=>EN<='0'; ——选中状态为S0、EN='0'
IF SP='1'THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S0;
END IF;
WHEN S1=>EN<='1'; ——选中状态为S1、EN='1'
IF SP='1'THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S2;
END IF;
WHEN S2=>EN<='1'; ——选中状态为S2、EN='1'
IF SP='1'THEN