基于FPGA的时间间隔测量仪的设计_毕业设计论文.doc

毕业设计说明书
基于FPGA的时间间隔测量仪的设计
2012年 6 月
摘要
随着科技的飞速发展,人们对高精度的时间频率的需求越来越高,传统可驯钟系统(自动校频系统)是模拟或半数字体制,其时差测量单元采用高精度时间间隔计数器,存在成本高、调试困难和不易建立模型等缺点。微电子技术的发展,推动了可编程逻辑技术的发展,出现了价格低廉、适合工程应用的现场可编程逻辑器件(FPGA),因此采用 FPGA 实现高精度时间间隔测量具有很大的现实意义。
本文详细分析了几种传统时间间隔测量方法,深入研究了延迟单元在 FPGA 中的实现方法,并对事件延迟内插法、时钟延迟内插法、以及差分延迟内插法三种时间内插法的仿真验证,结果表明,基于差分延迟线测量的分辨率最高,消耗硬件资源最少。在此基础之上,在 Altera公司CycloneII系列的EP2C8Q208C8N芯片中实现分辨率为43ps的差分延迟链,采用粗细结合测量的方案,设计了一个集成在 FPGA 内的高精度时间间隔测量模块。设计主要包括四个部分:系统时钟模块、粗测量单元、细测量单元、数据处理与数据传输模块,并在QuartusII开发环境下通过VerilogHDL语言对模块进行软件实现。
基于FPGA的时间间隔测量的精度达到200ps,具有高精度、集成度高、易于移植的特点,是一种较优的设计方案,有着很好的应用前景。
关键词:FPGA,时间间隔测量,差分延迟内插法,延迟线
ABSTRACT
With the rapid development of science and technology,the demand of high-precision time and frequency are increasingly traditional Disciplined Clock System (adaptive frequency calibration system) adopts analog or semi-digital system,which use high precision time-interval counter measure time it exists ing such as:high cost,large impact by environmental of microelectronics technology,and promote the development of programmable logic has been a low price, suitable for engineering applications of field programmable gate array (FPGA). So reaching precise time-interval measure based on FPGA has the great practical significance.
This paper analysis monly methods of time-interval. And the event delay interpolation method,the clock delay interpolation and the interpolation of three differential delay time interpolations of the simulation results show that the differential delay line based on the highest resolution measurements, a minimum consumption of hardware this basis,I design to realizing a 43ps delay difference of differential delay based on Cyclone II series of Alteras’EP2C8Q208C8N integrated high-precision time interval measurement module be designed and embedded in determine the specific measurement for time interval:design by crude and fine main m