EDA重点.doc

根据下图写程序:
2、阅读下列VHDL程序,画出相应RTL图:
LIBRARY IEEE;
USE ;
ENTITY three IS
PORT
(
clk,d : IN STD_LOGIC;
dout : OUT STD_LOGIC );
END THREE;
ARCHITECTURE bhv OF three IS
SIGNAL tmp: STD_LOGIC;
BEGIN
P1: PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
Tmp <= d;
dout <= tmp;
END IF;
END PROCESS P1;
END bhv;

3、VHDL程序填空:
下面程序是参数可定制带计数使能异步复位计数器的VHDL描述,试补充完整。
-- N-bit Up Counter with Load, Count Enable, and
-- Asynchronous Reset
library ieee;
use ;
use .all;
use ;
entity counter_n is
variable q (width : integer := 8);
port(data : in std_logic_vector (width-1 downto 0);
load, en, clk, rst : in std_logic;
q : out std_logic_vector ( 7 downto 0));
end counter_n;
architecture behave of counter_n is
signal count : std_logic_vector (width-1 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
count <= ; ――清零
elsif then ――边沿检测
if load = '1' then
count <= data;
en = '1' then
count <= count + 1;
end ;
end if;
end process;
;
end behave;
4、VHDL程序改错:(10分)
仔细阅读下列程序,回答问题
LIBRARY IEEE; -- 1
USE ; -- 2
ENTITY LED7SEG IS -- 3
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- 4
CLK : IN STD_LOGIC; -- 5
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); -- 6
END LED7SEG; -- 7
ARCHITECTURE one OF LED7SEG I