EDA十一最终结果.doc

LIBRARY IEEE;
USE ;
USE ;
USE ;
LIBRARY ALTERA;
USE ;
ENTITY MIMASUO IS
PORT
(CLK_4M :IN STD_LOGIC;
SS, KS :IN STD_LOGIC;
RST :IN STD_LOGIC;
G,M :IN STD_LOGIC;
A0,A1,A2,A3 :IN STD_LOGIC;
ENLOCK :OUT STD_LOGIC;
NUMB_CNT :OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
OUT_NUMB :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FM ,BJ :OUT STD_LOGIC;
STL :OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEGOUT :OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END MIMASUO;
ARCHITECTURE MIMA_G OF MIMASUO IS
SIGNAL CLK :STD_LOGIC;
SIGNAL N :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL FN :STD_LOGIC;
SIGNAL ACC :STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL REG :STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL NC :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL DB :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SEG :STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CNT8 :STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
OUT_NUMB <=N;
NUMB_CNT <=NC;
SEGOUT(6 DOWNTO 0)<=SEG;
COUNTER:BLOCK
SIGNAL Q:STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SEL:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
P1:PROCESS(CLK_4M)
BEGIN
IF CLK_4M'EVENT AND CLK_4M='1' THEN
Q<=Q+1;
END IF;
E