Lattice LCMXO2280 MachXO Mini评估开发方案.docx

Lattice LCMXO2280 MachXO Mini 评估开发方案关键字:工业控制,医疗电子,汽车电子,通信,消费电子 Lattice 公司的 MachXO 系于是非易失可无限次配置的可编程逻辑器件(PLD), 具有 256 到 2280 个 LUT,I/O 数多达 271 个, 多达 sysMEM 嵌入区块 RAM(EBR) 和多达 b 的分布式 RAM, 支持 IEEE 标准 边界扫描,,, 或 . 主要用在低密度的工业控制, 医疗电子, 汽车电子, 通信和消费电子等领域. 本文介绍了 MachXO 系列主要特性以及 MachXO ? Mini 开发套件主要特性与 MachXO ? Mini 评估板方框图,电路图和材料清单. The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted ina broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFR TM technology) and a low power sleep mode, all ina single-device. Designed for a broad range of low density applications including system control designs, the MachXO PLD family is used ina variety of end markets including consumer, automotive, communications, computing, industrial and medical. The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER ? design tools from Lattice plex designs to be efficiently implemented using the MachXO family of devices. Popular lo