ic datasheet pdf-54act16823,74act16823,pdf(18-bit bus interface flip-flops).pdf

54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
D Members of the Texas Instruments 54ACT16823 . . . WD PACKAGE
Widebus Family 74ACT16823 . . . DL PACKAGE
(TOP VIEW)
D Inputs Are TTL-patible
D Provide Extra Data Width Necessary for
1CLR 1 56 1CLK
Wider Address/Data Paths or Buses With
1OE 2 55 1CLKEN
Parity
3 54
D 1Q1 1D1
Flow-Through Architecture Optimizes PCB GND 4 53 GND
Layout 1Q2 5 52 1D2
D Distributed VCC and GND Pin Configuration 1Q3 6 51 1D3
Minimizes High-Speed Switching Noise VCC 7 50 VCC
D EPIC(Enhanced-Performance Implanted 1Q4 8 49 1D4
CMOS) 1-µm Process 1Q5 9 48 1D5
D Package Options Include Plastic 300-mil 1Q6 10 47 1D6
Shrink Small-Outline (DL) Packages Using GND 11 46 GND
25-mil Center-to-Center Pin Spacings and 1Q7 12 45 1D7
380-mil Fine-Pitch Ceramic Flat (WD) 1Q8 13 44 1D8
Packages Using 25-mil Center-to-Center 1Q9 14 43 1D9
Pin Spacings 2Q1 15 42 2D1
2Q2 16 41 2D2
description 2Q3 17 40 2D3
GND 18 39 GND
These 18-bit flip-flops feature 3-state outputs 2Q4 19 38 2D4
designed specifically for driving highly-capacitive 2Q5 20 37 2D5
or relatively low-impedance loads. They are 2Q6 21 36 2D6
particularly suitable for implementing wider buffer V 22 35 V
registers, I/O ports, parity bus interfacing, CC
2Q7 23 34 2D7
working registers.
2Q8 24 33 2D8
The ’ACT16823 can be used as two 9-bit flip-flops GND 25 32 GND
or one 18-bit flip-flop. With the clock-enable 2Q9 26 31 2D9
(CLKEN) input low, the D-type flip-flops enter data 2OE 27 30 2CLKEN
on the low-to-high transitions of the clock. Taking 2CLR 28 29 2CLK
CLKEN high disables the clock buffer, thus
latching the outputs. Taking the clear (CLR) input
low causes the Q outputs to go low independently
of the clock.
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low
logic levels) or a h