ic datasheet pdf-adc12c080,pdf datasheet (12-bit, 65_80 msps a_d converter).pdf

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August 2007
ADC12C080
12-Bit, 65/80 MSPS A/D Converter
General Description Features
The ADC12C080 is a high-performance CMOS analog-to- ■ 1 GHz Full Power Bandwidth
digital converter capable of converting analog input signals ■ Internal reference and sample-and-hold circuit
into 12-bit digital words at rates up to 80 Mega Samples Per
Low power consumption
Second (MSPS). This converter uses a differential, pipelined ■
architecture with digital error correction and an on-chip sam- ■ Data Ready output clock
ple-and-hold circuit to minimize power consumption and the ■ Clock Duty Cycle Stabilizer
ponent count, while providing excellent dynamic ■ Single + supply operation
performance. A unique sample-and-hold stage yields a full-
■ Power-down mode
power bandwidth of 1 GHz. The ADC12C080 may be oper-
32-pin LLP package, (, pin-pitch)
ated from a single + power supply and consumes low ■
power. A separate + supply may be used for the digital
output interface which allows lower power operation with re- Key Specifications
duced noise. A power-down feature reduces the power con- ■ Resolution 12 Bits
sumption to very low levels while still allowing fast wake-up
■ Conversion Rate 80 MSPS
time to full operation. The differential inputs accept a 2V full
SNR (f = 170 MHz) 68 dBFS (typ)
scale differential input swing. A stable internal voltage ■ IN
SFDR (f = 170 MHz) 86 dBFS (typ)
reference is provided, or the ADC12C080 can be operated ■ IN
with an external reference. Output data format (offset ■ Full Power Bandwidth 1 GHz (typ)
binary versus 2'plement) and duty cycle stabilizer are ■ Power Consumption 300 mW (typ)
pin-selectable. The duty cycle stabilizer maintains perfor-
mance over a wide range of clock duty cycles. Applications
The ADC12C080 is available in a 32-lead LLP package and ■ High IF Sampling Receivers
ope