异步信号的同步化.pdf

designfeature By Mike Stein, Paradigm Works
AS DIGITAL DESIGN BECOMES INCREASINGLY SOPHISTICATED,
CIRCUITS WITH MASIC or FPGA library
The first step in managing multiclock designs is has timing requirements to help you determine the
to understand the problem of signal stability. When window of vulnerability.“Setup time” describes the
a signal crosses a clock domain, it appears to the cir- time an input signal to a flip-flop must be stable be-
cuitry in the new clock domain as an asynchronous fore the clock edge. “Hold time” is the time the sig-
signal. The circuit that receives this signal needs to nal must remain stable after the clock edge. These
synchronize it. Synchronization prevents the meta- specifications are usually conservative to account for
stable state of the first storage element (flip-flop) in all the possible variations in supply voltage, operat-
the new clock domain from propagating through the
circuit. NO COMBINATIONAL LOGIC HERE
Metastability is the inability of a flip-flop to arrive CLOCK 1 DOMAIN CLOCK 2 DOMAIN
at a known state in a specific amount of time. When
DATA DQSET DQSET DQSET
a flip-flop enters a metastable state, you can predict OUTPUT
neither the element’s output voltage