eda实验2位十进制.doc

实验名称:2位十进制频率计
实验目的:设计2位十进制频率计,学习较复杂的数字系统设计方法。
实验内容:源程序
十进制
library ieee;
use ;
use ;
t10 is
port (clk,rst,en:in std_logic;
dout:out std_logic_vector(3 downto 0));
t10;
architecture behav t10 is
begin process(clk,rst,en)
variable q:std_logic_vector(3 downto 0);
begin if rst='0' then q:=(others=>'0');
else if (clk'event and clk='1') then
if en='1'then if q<9 then q:=q+1;else q:="0000";
end if;end if;end if;end if;
dout<=q; end process; end behav;
模拟图形:

测控计
library IEEE ;
use ;
use ;
entity chekong is
port (CLK : in std_logic;
EN,RST,Load :out std_logic );
end chekong;
architecture behav of chekong is
signal CLK2 : std_logic;
begin process(clk)
begin if clk'event and clk ='1' then
CLK2 <= not clk2;
end if;end process;
process(clk,clk2)
begin if clk='0'and clk2='0' then rst<='1';
else rst<='0';end if;
end process;Load <= not CLK2;EN <=CLK2;end behav;
模拟图:

library ieee;
use ;
entity jicunqi is
port(clk : in std_l