Viterbi译码器低功耗设计.pdf

重庆大学硕士学位论文英文摘要IIABSTRACTConvolutinal coding is a coding scheme often employed in digital decoders are used to decode convolutional decoders employed in digital munications plex anddissipate large power. With the proliferation of battery powered devices such ascellular phones and puters, power dissipation, along with speed and area, isa major concernin VLSI design. In this thesis, we investigated a low-power design ofViterbi decoders munications CMOS technology the major source of powerdissipation is attributed todynamic power dissipation, which is due to the switching of signalvalues. The focusof our research in the low-power design of Viterbi decoders is reduction of dynamicpower dissipation at logic level in the standard cell design VD posed of four functional units:1)Thebranch metrics unit(BMU);2)pare-select unit(ACS);3)Thepath metrics unit(PMU);4)Thesurvivor memory unit(SMU);Regarding the power dissipation of the Viterbi decoder, the SMU is the hottestspot in the Viterbi decoder dueto the frequent memory are twotraditional techniques for the realization of survivor memory unit in viterbidecoder--register exchange(RE) and trace back (TB) method. RE has a plicatedinterconnections and needs a high power consumption .TB needs a largequantity of buffers and has long decoding delay. In this paper a modifiedregister-exchange (RE) method is presented,which reduce its memory access rate andits amount of memory, thus, reduces the power on the modifiedregister-exchange (RE) method SMU,a Low power viterbi decoder can be experimental result shows the proposed design reduces thedynamicpowerdissipation of a Viterbi decoder by pared with theonewithoutconsidering the low-power :ViterbiDecoder,Low Power Consumption,SurvivalMemoryManagement,RegisterExchange重庆大学硕士学位论文1绪论1信源信源编码器信道编码器信道噪声源信道译码器信源译码器信宿解调器调制器??sC??sC%??S??m??C??E???S???m??