《内容提要》ppt课件.ppt

VHDL3BASICOPERATORSANDARCHITECTUREBODYDesigndescriptions&Designconstructionsexamplesaretakenfromfoundationseriesexamplesexercise3:VHDL()*)Structural2)Dataflow3)BehavioralUseofsignalsandvariablesexercise3:VHDL()*:VHDL()*:VHDL()*,or,nand,nor,xor,xnor,not--::Drawthetruthtabletoshow(AnandB)nandC≠Anand(BnandC)Relationoperators=equal;/=notequal< <= > >=smaller,bigger,:VHDL()*:Fillin“?__”.ItshowstheNAND-gateisnotassociative,soAnandBnandCisillegal.(AnandB)nandC≠Anand(BnandC)exercise3:VHDL()*StudentID:__________________Name:______________________Date:_______________(Submitthisattheendofthelecture.)seeVHDLforEngineers–(Googlebooks)-puters-685LogicalshiftandrotateSll(shiftleftlogical,fillblankwith0);srl(shiftrightlogical,fillblankwith0)rol(rotateleftlogical);ror(rotaterightlogical).“10010101”rol3is“10101100”Arithmeticshift(http://en./wiki/Arithmetic_shift)sla(shiftleftarithmetic)fillblankwith0,sameassll(shiftleftlogical)sra(shiftrightarithmetic),fillblankwithsignbit(MSB)exercise3:VHDL()*<=“10010101”;Asll2=__________Asrl3=__________Asla3=__________Asra2=__________Arol3=__________Aror5=__________exercise3:VHDL()*‘+’arithmeticadd,forinteger,float.‘-’arithmeticsubtract,forinteger,float.‘&’concatenation:‘0’&‘1’is“01”,Noticetheuseof“&”.exercise3:VHDL()*‘*’multiplication‘/’division‘mod’=modulus==A-(B*N)--Nisaninteger‘abs’=absolutevalue‘**’=exponentiationexercise3:VHDL()*10.