PLL论文——A 90-nm CMOS 5-GHz Ring-Oscillator PLL.pdf

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 5, MAY 2013 1151 A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation Seungkee Min , Member, IEEE ,TinoCopani , Associate Member, IEEE , Sayfe Kiaei , Fellow, IEEE ,and Bertan Bakkaloglu , Senior Member, IEEE Abstract— Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLL s. However, due to their supply noise sensitivity and high noise ?oor, their applications have been limited to low-performance applications. The proposed archi- tecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that ex tracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperat ure variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noi se cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at -GHz frequency. The measured phase noise at 1-MHz offset after cancellation is 105 dBc/Hz. The proposed RO-PLL is fabricated in 90-